1. Field
Example embodiments relate to a non volatile memory device and a memory system having the same. In particular, example embodiments relate to a non volatile memory device which has a 1 transistor (1T) DRAM as a buffer memory and a memory system having the same.
2. Description of the Related Art
A semiconductor memory device may be generally classified as a volatile memory device or a non volatile memory device. Types of volatile memory devices include a dynamic random access memory (DRAM) and a static random access memory (SRAM), whereas types of non volatile memory devices include an erasable programmable read only memory (EPROM), an electrical erasable programmable read only memory (EEPROM), and a flash memory.
Flash memory is recently attracting attention as a non volatile memory, which may be used as a substitute for other conventional storage devices because it has a small size and a large capacity. Types of conventional flash memories include a NOR flash memory in which a plurality of memory cells are arranged in parallel between a bit line and a ground line and a NAND flash memory in which a plurality of memory cells are serially arranged between the bit line and the ground line. The NOR flash memory generally provides a fast read operation since a NOR flash memory has a parallel structure and thus, can directly access a desired memory cell. The NAND flash memory has high integration characteristics compared to the NOR flash memory. A conventional flash memory device is a device which includes the NOR flash memory and/or the NAND flash memory to store data.
FIGS. 1A to 1C show conventional non volatile flash memory devices. FIG. 1A is a block diagram of a conventional NOR flash memory device, FIG. 1B is a block diagram of a conventional NAND flash memory device, and FIG. 1C is a block diagram of a conventional OneNAND flash memory device.
The conventional NOR flash memory device is described below with reference to FIG. 1A. Referring to FIG. 1A, a NOR flash cell array 11 has a NOR flash memory structure. A NOR interface 16 may perform an information converting operation and an input/output operation in order to exchange various information with an external device. The NOR interface 16 may transfer an address ADD and a command Corn received from an external device to a controller 14. The NOR interface 16 may output data Data supplied by a data path 12 to the external device during a read operation, and may output data Data received from the external device to a write buffer 15 during a write operation. The controller 14 may output various control signals such as a read control signal and a write control signal to control the NOR flash memory device in response to the address ADD and the command Com and may transmit the address ADD to a control signal and address path 13. The control signal and address path 13 may decode the address ADD received from the controller 14 to select a corresponding memory cell of the NOR flash cell array 11. The control signal and address path 13 may control the selected memory cell of the NOR flash cell array 11 in order to input and/or output data Data in response to the control signal. The data path 12 may output data Data of the selected memory cell to the NOR interface 16 during the read operation, and may transmit data Data from the write buffer 15 to store the data Data in the selected memory cell during the write operation. The write buffer 15 may receive data Data from the NOR interface 16, temporarily store the data Data and then output the data Data to the data path 12 during the write operation. During the read operation, the NOR flash memory device may directly access a memory cell of the NOR flash cell array 11 to output data, and thus the NOR flash memory device generally has a fast operation speed. However, the NOR flash memory device performs write and/or erasing operation in a block unit having a number of memory cells, and so the write buffer 15 is used during the write and/or erasing operations in order to reduce an operation speed difference with the external device.
In the NAND flash memory device of FIG. 1B, a NAND flash cell array 11 has a NAND flash memory structure. A controller 24 and a control signal and address path 23 operate in substantially the same manner as the controller 14 and the control signal and address path 13 previously described with respect to FIG. 1A. A NAND interface 26 also performs an information converting operation and an input/output operation in order to exchange various information with the external device. However, the NOR interface 16 and the NAND interface 26 differ in designated protocol.
The NAND flash memory device operates based on a page unit having a number of memory cells during the read operation as well as the write and erasing operations, and thus includes a page buffer 25 in order to reduce an operation speed difference with the external device. The page buffer 25 may receive data Data from the NAND interface 26, temporarily store the data DATA, and then output the data Data to the data path 22 during the write operation. The page buffer 25 may also temporarily store data Data from the data path 22 and output the Data to the NAND interface 26 during the read operation.
FIG. 1C shows the OneNAND flash memory device. Generally, a conventional NAND flash memory has a slow driving speed because memory cells are serially connected and slow operation speed because the NAND flash memory reads data in a page unit. A conventional NOR flash memory device has a fast driving speed because memory cells are connected in parallel and a fast operation speed because the NOR flash memory device can directly access a selected memory cell. However, a conventional NOR flash memory device generally has low integration. The conventional OneNAND flash memory includes a NAND flash cell array 31 which has high integration as a cell array and a NOR interface 36 for exchanging information with the external device. The OneNAND flash memory includes a buffer memory 35 in order to overcome a speed difference and a processing unit (e.g., block, page, and memory cell) difference during read and write operation between the NAND flash cell array 31 and the NOR interface 36. A SRAM which is fast in operation speed is usually used as the buffer memory 35.
As shown in FIGS. 1A to 1C, there exist various interfaces 16, 26 and 36 for a flash memory device among the conventional non volatile memory devices. In order to drive various non volatile memory devices, the external device should have various memory controllers. In particular, in case of driving the volatile memory devices, as well as the non volatile memory devices, the types of memory controllers that the external device generally includes is increased.
FIG. 2 is a block diagram illustrating a memory system having a conventional volatile memory device and a conventional non volatile memory device.
A first non conventional volatile memory device 41 and a second conventional non volatile memory device 42 shown in FIG. 2 are different in type and may be EPROMs, EEPROMs, or various flash memory devices, for example. Thus, the first non volatile memory device 41 and the second non volatile memory device 42 have different interfaces. A volatile memory device 43 is a DRAM or a SRAM, for example.
Because the first and second non volatile memory devices 41 and 42 and the volatile memory device 43 have different interfaces, the memory system shown in FIG. 2 has a different controller for each of the memory devices. Thus, the memory system of FIG. 2 includes a first non volatile memory device controller 51 for the first non volatile memory device 41, a second non volatile memory device controller 52 for the second non volatile memory device 42, and a volatile memory device controller 53 for the volatile memory device controller 43.
A memory bus 60 may transmit data and commands between the memory devices 41, 42 and 43 and the corresponding memory device controllers 51, 52 and 53.
That is, as shown in FIG. 2, the conventional memory system has a plurality of memory controllers 51, 52 and 53 to individually control the memory devices 41, 42 and 43, and thus has low efficiency because the conventional memory system is large in size, high in power consumption and high in price.
In order to solve the above problems of a conventional memory system, such as the one shown in FIG. 2, a non volatile memory device which has a volatile memory cell such as a DRAM or SRAM as a buffer memory to unify the interface has been suggested. However, this conventional solution has a problem in that there is a limitation to an applicable memory type and may result in an increase in the size of the memory device.
Further, a memory cell of a DRAM typically includes one transistor and one capacitor. Discrimination on whether data is “0” or “1” depends on whether the capacitor is charged or not. That is, the existing DRAM must have the capacitor to store the data.
However, in the semiconductor memory device which pursues high integration, the memory cell having such a capacitor becomes an obstacle which makes it difficult to reduce the layout area size of the semiconductor memory device.